1. Field of the Invention
The present invention relates to semiconductor design, and more particularly to a hierarchical system and method for VLSI design.
2. Discussion of Related Art
The design of a Very Large Scale Integration (VLSI) layouts comprises manufacturing layout verification, layout modifications, and verification of design conventions.
Layout verification involves the checking a layout against the design rules (DRC) and a comparison of extracted circuitry against a schematic netlist (LVS).
Layout modifications enhance timing, reliability, and/or manufacturability. A modification is an alteration of the layout without alteration of the logical behavior of the circuitry. Modification steps includes cheesing, i.e., creating patterns of holes, in wide metal areas and filling of spaces to provide uniform density. Modification includes adding redundant vias, and optical proximity correction and other resolution enhancement techniques. Layout modification may be constrained to preserve the existing hierarchy. If not, layout modification has the freedom to exploit rearranging the hierarchy. The degree of freedom available depends on the application.
Methodology checks verify design conventions, e.g., labeling standards for the layout or the observation of contact zones of macros.
An engine for VLSI layout processing has to provide functionality that implements layout verification and modification tasks efficiently. Two mechanisms help in this task.
The hierarchical representation of the VLSI design avoids redundant computations and independent subproblems allow parallel processing.
A VLSI layout processing task, called VLPT, is a composition of basic operations, e.g., expand and shrink, on VLSI design objects, e.g., shapes or levels. Typically the description of a VLPT is given in a high level programming language. The high level language operates primarily on pointsets, attributes, hierarchical structure and concepts derived from interaction principles, e.g., nets based on electrical connectivity (see FIG. 1).
Therefore, a need exists for a system and method for automated hierarchical VLSI design having improved efficiency.